1. Field
One or more example embodiments of the following description relate to an arithmetic processing apparatus and method for processing an application at a high speed, and more particularly, to an apparatus and method for quickly executing an application by processing an application code and an application operation necessary for driving of the application in a parallel manner.
2. Description of the Related Art
A processing apparatus such as a high-performance processor, a digital signal processor (DSP), and a graphic processing unit (GPU) accelerates operation using a particular computing device that processes an algorithm at a high speed. For example, the particular computing device may include single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD), a hardware accelerator, and the like. Here, the SIMD refers to a parallel computing method to process several units of data with one instruction. The MIMD refers to a parallel operation method to process several units of data with a plurality of instructions.
When using the SIMD, the MIMD, and the like, a program control device and the particular computing device are alternately operated to execute an application operation.
Here, since the program control device maintains an idle state during operation of the particular computing device, execution of the application may be delayed. In the same manner, the particular computing device may maintain an idle state while the program control device is executing the application operation or an application code, thereby causing a delay in execution of the application.
In addition, during idle states of the program control device and the particular computing device, hardware may be wasted and accordingly the efficiency of the processing apparatus may be reduced.